The continuous shrinking in dimensions of electronic devices utilized in ULSI circuits in recent years has resulted in increasing the resistance of the BEOL metallization. The wiring capacitance increases due to the intralayer and interlayer dielectric. This combined effect increases signal delays in ULSI electronic devices. In order to improve the switching performance of future ULSI circuits, low dielectric constant (k) insulators and particularly those with k significantly lower than silicon oxide are needed to reduce capacitance. The low k dielectric materials (i.e. low k dielectrics) that have been considered for applications in ULSI devices include materials containing elements of Si, C, O and H, such as methylsiloxane, methylsilsesquioxanes, and other organic and inorganic polymers. Such materials can be deposited by means of spin-coating or Plasma Enhanced Chemical Vapor Deposition (PECVD).
One of the problems encountered when these materials are integrated into BEOL interconnect wiring structures is that they have the tendency to crack, especially in high humidity environments. The driving force for cracking is proportional to the square of the biaxial stress present in the low k dielectric layer. Reducing biaxial stress is very important for minimizing cracking in a low k dielectric layer
Despite years of work on low and ultralow k dielectric materials, there is a continued need for developing methods for controlling and reducing the biaxial stress in low and ultralow k dielectric layers and designing tools intended for the fabrication of low and ultralow k dielectric layers with low and controllable biaxial stress at room temperature and at the operating temperature of the intended devices that will comprise such layers.